1. Field of the Invention
The present invention pertains to the field of digital communications. More particularly, this invention relates to switching hubs for high speed local area networks.
2. Background
Ethernet is a specific implementation of what is generally referred to as a Carrier Sense Multiple Access/Collision Detection (CSMA/CD) protocol. In accordance with such protocols, only a single station is permitted to have access to the medium at any one time. A procedure is specified to resolve conflicts resulting from concurrent access attempts by multiple sources. For Ethernet, the details of this protocol are defined by the IEEE 802.3 specification.
A typical prior local area network is comprised of a set of communication agents coupled to a common communication medium. For example, an Ethernet local area network comprises a set of Ethernet compatible communication agents coupled to a coaxial, twisted pair, or fiber optics cable as a communication medium. In such systems a communication transaction between any two of the communication agents typically prevents communication among the other communication agents during the communication transaction.
One prior method for increasing the capacity of a local area network is to employ bridge circuits. Prior art bridge circuits typically couple together segments of local area networks. Typically, each segment comprises a set of communication agents coupled to a communication medium. A bridge circuit enables communication between each of the communication mediums.
Such prior are bridge circuits typically listen for communication messages on each of the communication mediums and propagate the appropriate communication messages to the other communication medium according to the network configuration. Communication messages are commonly referred to as communication frames.
Such a prior are bridge circuit typically buffers communication frames that require propagation to another communication medium. Thereafter, the bridge circuit forwards the buffered communication frames to the appropriate destination communication agents. Unfortunately, such buffering and forwarding of communication frames between communication mediums of the local area network increases the overall latency in the communication network.
Another prior art method for increasing the capacity of a local area network is to employ a switched hub circuit. A switched hub circuit is typically arranged in a xe2x80x9cstarxe2x80x9d configuration wherein each segment of the local area network coupled to a unique serial communication port of the switched hub circuit. The switched hub circuit typically senses incoming communication frames, determines the destinations of the incoming frames, and switches the incoming communication frames to the appropriate outbound transmission paths.
Such switched hub circuits typically allow parallel data transfer between ports as long as the data transfer paths do not conflict.
Unfortunately, the switching functions performed by such prior art switched hub circuits are complicated by certain types of communication traffic. For example, if more than one communication agent attempts to transmit to the same communication agent, the switched hub circuit must select one of the transmissions and delay the other transmissions. The delayed transmissions increase the latency in the network.
In addition, broadcast transmissions and multicast transmissions require a switched hub circuit to switch a single incoming communication frame to multiple destination communication agents even though conflicting traffic may be under way to the destination communication agents. The multicast transmissions typically conflict with other transmissions, thereby increasing delays in the network.
The data transmitted in the network physical medium is in a serial form. However in most switched hubs the data is transformed (demultiplexed) to a slower multi-bit parallel format. This conversion is necessary to enable storage of the data in memory devices in the standard format of bytes and words. This conversion is also required in order to match the data rate to the read/write speed of memories and other processing devices. For this purpose and particularly when the serial data rate is 100 megabit/sec or above, the data is converted to a 32 or even 64 bits parallel format.
In most prior switched hubs the inbound data is stored, at least temporarily, in the receiving memory. This data is then transferred to the destination port circuitry for processing and subsequent transmission. The data transfer either involves a plurality of data buses and a switching mechanism between these buses, or a common bus shared by all port circuits. A typical prior art switched hub is shown in FIG. 1. In such a prior art switched hub, network segments b 1-n are each coupled to a corresponding packet processing unit (PPU) 3 which in turn are coupled to cross bar switching matrix 1. Each PPU includes a transmitter 8, a receiver 9, a media access controller 10, a multiplexor 13a and a demultiplexor 13b. 
One object of the present invention is to provide a switching hub for a high speed communication network, especially Fast Ethernet and Gigabit Ethernet. Another object of the present invention is to provide a switching hub for a communication network that resolves conflicts among inbound communication frame that specify the same destination, thereby preventing collisions in the network.
Another object of the present invention is to provide a switching hub for a communication network that performs broadcast and/or multicast operations while avoiding collisions with conflicting communication traffic. Another object of the present invention is to provide a switching hub for a communication network that provides a flexibility in the switching hub makeup and enables system sizing and type alteration by means of replacing modules connected to a common motherboard.
These and other objects of the invention are provided by a communication system including a switched hub circuit that transfers incoming communication frames via a set of serial communication links. The switched hub circuit stores the incoming communication frames into a set of memory buffers that supply a set of outbound communication frames for transfer over the serial communication links. The switched hub circuit includes the means to decipher the destination of each message and a crossbar type switching matrix in the outbound physical layer to route the outbound transmission to the desired destination.
Other objects, features and advantages of the present invention will be apparent from the accompanying drawings, and from the detailed description that follows below.
In general, in one aspect, the invention features an apparatus for interconnecting N network segments each of which operates in accordance with a defined bus protocol such as IEEE 802.3 or similar protocols. The apparatus includes N physical interfaces to network segments, N Packet Processing Units (PPUs) 23, a Routing Controller (RC) 21, a Switching Matrix (SM) 1, an Address Management Unit (AMU) 17 and a Packet Broadcast Controller 20, as illustrated in FIG. 2. The input from each of the N network segments 6 connects to the input port of the corresponding Packet Processing Unit 23. The output port of each of the Packet Processing Units connects to a corresponding input in the Switching Matrix. The outbound line of each of the network segments connects to the corresponding output in the Switching Matrix. The Address Management Unit 17 and the Routing Controller 21 connect to all the Packet Processing Units via a multi-bit parallel bus 4. The Routing Controller connects to the switching matrix 1 and controls its operation.
Each Packet Processing Unit receives packets from the network segment 6, decodes the packet""s source and destination addresses, and forwards this information to the Address Management Unit. When instructed by the Routing Controller 21, the Packet Processing Unit 23 retransmits the packet to the Switching Matrix 1 which provides a physical connection between PPU 23 and network segment 6. The Packet Processing Unit includes a Receiver 9, a Transmitter 8, a Media Access Controller (MAC) 10, and Memory 12, as illustrated in FIG. 3. The output of the Receiver connects to the input of the Media Access Controller. The Media Access Controller""s Data Output Bus 14 connects to the memory""s input, and the memory""s output connects to the Media Access Controller""s Data Input Bus 13. The MAC and memory are controlled by the Packet Processing Unit Controller (PPC) 11. The Receiver 9 decodes the data from the network and partitions it as 8 bit parallel data. The Media Access Controller 10 deciphers messages, detects collisions and errors, extracts packet addresses, maintains statistics, formats and sends out packets to the Transmitter, and provides xe2x80x9celasticityxe2x80x9d buffers between the received data clock and the system clock. The Transmitter 8 takes the 8 bit parallel data from the MAC and transmits it as serial Manchester-encoded data. The Memory 12 is used for temporary storage of packets between the packet reception and the time the Packet Processing Unit 23 is instructed to send out the data. The Packet Processing Unit Controller 11 controls the MAC, keeps track of packets in memory, and interfaces to the Address Management Unit 17 and the Routing Controller 21. The transmitter 8, receiver 9 and MAC 10 are implemented as in their like numbered counterparts in prior art PPUs 3 as shown in FIG. 1.
The Switching Matrix 1 is constructed as a crossbar switch having N input signal paths (each carrying a single signal) and including Nxc3x97N switching elements, each with an input and an output. Each switch element can connect one input to one output. Multiple switch elements can be activated simultaneously to connect multiple inputs to multiple outputs. This allows for a maximum of N connections between inputs and outputs at any one time. The use of the Switching Matrix increases the throughput of the switch to N times the throughput of any one network segment. The Switching Matrix is controlled by the Routing Controller 21 which receives the routing requests from the PPC 11 and activates the required connection between an input and an output when the requested output is inactive.
The PPC 11 receives the source and destination addresses of each packet from the MAC 10. The source addresses is stored in an address list that identifies the network segment associated with each address. The PPC searches its address list for the destination address of the packet and outputs a code identifying the path needed in the Switching Matrix 1 to transmit the packet to its destination network segment. The PPC sends new source addresses it received to the Address Management Unit 17 which distributes that source address to all the other PPCs. The PPC also sends Broadcast packets to the Broadcast Controller 20 which distributes those packets to all other PPCs.
In many networking protocols, such as Ethernet and Fast Ethernet, every packet contains two unique addresses: one address identifies the destination agent and one address identifies the source agent. One method of increasing network throughput is to xe2x80x9csegmentxe2x80x9d the network by physically dividing it into multiple sections, each containing a unique subset of the agents on the original network. Without segmentation every packet is routed to every agent and therefore only a single packet can be transmitted on the whole network at any given time limiting the network throughput. With segmentation, the throughput of each segment is limited only by the traffic on that segment, not by the total network traffic.
The invention presented here increases the packet capacity of a network by supporting network segmentation with N simultaneous inter-segment connections and by implementing advanced packet filtering. N simultaneous inter-segment connections are achieved using a Switching Matrix that allows N simultaneous electrical connections. Each connection provides a path from the inbound line of the source segment to the outbound line of the destination segment. Each PPU receives on its segment, and decodes the source and destination addresses of each packet received. When both addresses are on the same network segment, the packet is local to the segment and the packet is not forwarded. When the destination address segment differs from the source address segment, the switch generates an electrical connection between the output port of the receiving Packet Processing Unit and the outbound physical medium of the destination network segment. Once such an electrical connection is established, the packet is retransmitted from the receiving PPU to its destination network segment.
In the meantime the content of the packet is stored in a memory for temporary keep.
To facilitate the apparatus functionality, a packet received as a single line serial data signal on the input port of the receiver of a PPU is typically Manchester encoded but other codes may be used. The signal is first decoded and multiplexed into a parallel format, typically but not necessarily 8 bits wide. This data is next processed in the MAC where the source and destination addresses are extracted and sent to the PPC 11. In the meantime the content of the packet is stored in a temporary storage while routing is determined. In the PPC, the requested destination address is compared with the complete list of known source addresses. If the destination address is found on the list and it is on a different segment than the packet""s source address, a code is sent to the Routing Controller requesting a connection between the receiving PPUs output and the destination segment. The routing controller waits until the destination segment is not busy and then makes the electrical connection to the destination and commands the receiving PPU to recall the stored packet from memory and start the data retransmission.
In the cases where the PPC is unable to determine the transmission path of a received packet because it is not in its lookup table, it will tag that packet as a Broadcast packet, bound to be sent to all the network""s segments. In prior art switches using Crossbar switching matrices such Broadcast transmission is performed by connecting all the output ports to a single inputs which originated the broadcast packet, and then transmitting that packet to all the ports simultaneously. In this type of architecture the controller must wait for all the ports to stop their current transactions, and then hold the system in this state until the complete broadcast packet is transmitted. This operation blocks the entire switch for long periods of time and greatly reduces the data transfer rate capability of such switches.
In the invention presented here this problem is eliminated using the Broadcast Bus. Every time a packet is received with an unknown transmission path, it is sent to all the PPUs via the Broadcast bus. Each PPU receives the packet from the bus and transmits it through its serial output to the network segment to which it is connected. Since at all times each port is connected to one of the network segments, broadcast packets transmitted from all the PPUs are in fact transmitted to the network segments. This method does not block the switch while broadcasting and yet guarantees the broadcast to all the segments.
To enable each PPC to determine the transmission path of received packets all the PPCs must share a common data bus base for the locations of all the communication agents on the network. In the invention presented here each PPC contains its own list of destination transmission paths. In order to guarantee that the lists in all the PPCs are identical and updated the content of these lists is controlled by the Address Management Unit.
Per port switching capability was developed initially for 10 Mbit/sec. networks. Subsequently, increases in network speed required an ever growing level of multiplexing and intra switch bus width in order to accommodate the slower speed of memory devices used in the process and to allow adequate signal bandwidth to guarantee unimpeded data traffic. With the present invention, the per port switching technology can be efficiently and effectively extended to Fast Ethernet, Gigabit Ethernet and other high speed networks as well because the necessity for demultiplexing the entire packet is eliminated, and in all but a few cases, serial data received in the PPU is retransmitted from the same PPU which enables a modular and extendable system..
The prior state of the art may be best understood by referring to FIG. 1. Under the conventional approach to Ethernet network expansion, a very large bus or a plurality of smaller ones would have been necessary to provide per port switching capability on and between multiple network segments supported within a central switching hub. With the invention described herein, however, the switching matrix 1 that is currently used can provide N simultaneous inter-segment connections each carrying the maximum network data flow. A typical switching matrix of the type which could be used with the invention is shown in FIG. 5.
In prior art switches, the switching mechanism 1 is placed between the parallel output of the receiving MAC and the parallel input of the transmitting MAC. One aspect of the novelty of this invention is the placement of the switching matrix between the Manchester encoded serial output of the transmitting MAC and the outbound transmission line of the destination network segment. One advantage of this invention is that the received inbound data is processed and retransmitted in a single Packet Processing Unit and the routing and switching of that data to its final destination is done in the outbound transmission physical layer; each PPU is a stand alone circuit where, except in the case of broadcast, data is transferred into the port and out of the port through single line interfaces only. A Switching Hub based on this invention can be constructed as a motherboard with the port circuits as plug-ins to the motherboard. The number and size of buses on that motherboard is fixed and independent of the number or type of PPUs. The number of PPUs on a switching hub according to this invention depends only on the number of switching elements in the switching matrix used.
Other advantages and features will become apparent from the following description of the preferred embodiment and from the claims.